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Our is a very efficient
implementation of the Discrete Cosine Transform (DCT) algorithm and its
inverse (IDCT).
This transform is
utilized in the current standards for still images (JPEG) and video
compression (MPEG).
This IP can perform both DCT and IDCT on a 8x8 block
of samples. Precision of the input samples is 8 bits. Precision of the
transformed output is 11 bits. After a latency period, one samples is
transformed per clock cycle.
The performance and the size of this core vary with
the technology used for the implementation.
With 0.5 u, a size of about 12000 gates plus a
64x14 dual port RAM and a speed of around 50 MHz is readily
achievable.
Higher speed can be obtained with faster technologies or more gates.
Download the datasheet.
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